1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor memory device, and more particularly to a method for fabricating a triple well of a semiconductor memory device.
2. Description of the Related Art
Complementary metal oxide semiconductor (CMOS) dynamic random access memory (DRAM) devices are driven by a power source voltage V.sub.CC and a ground voltage V.sub.SS. In addition, a back bias voltage V.sub.BB is applied to the substrate in order to improve latch up immunity, cell isolation and operation speed. However, in a highly integrated semiconductor memory device such as a submicron device, the back bias voltage increases a short channel effect in N channel transistors. To solve this problem, a triple well structure has been suggested, in which the back bias voltage V.sub.BB is applied to a memory cell array region, and the ground voltage V.sub.SS is applied in a region of a peripheral circuit region in which N-channel transistors are to be formed, thereby improving the characteristics of the memory device.
A semiconductor memory device adopting such a triple well structure is shown in FIG. 1. Referring to FIG. 1, a first P-type well 110 and a second P-type well 120 in which N channel transistors are to be formed are formed on a P-type substrate. The N-channel transistors include gates 116 and 126, respectively formed on gate oxide films 114 and 124, and beside N-type impurity regions 112 and 122 which become source and drain regions, respectively. Also, a first N-type well 130, having a P-channel transistor, is formed in a peripheral circuit region. Here, the P-channel transistor includes P-type impurity regions 132 to be source and drain regions, a gate oxide film 134 and a gate 136.
The first P-type well 110 and the second P-type well 120 are separated by a second N-type well 140 enclosing the second P-type well 120. The second N-type well 140 has a sidewall region 142 extending vertically below the surface of the substrate 100 to a first depth, and a base region 144 which is formed laterally below the surface of the substrate 100 by a second depth and overlaps with lower portions of the sidewall region 142.
Thus, a back vias voltage V.sub.BB is applied to a P-type impurity region 128 formed in the second P-type well 120, and a ground voltage V.sub.SS is applied to a P-type impurity region 118 formed in the first P-type well 110. Also, a power source voltage V.sub.CC is applied to an N-type impurity region 138 formed in the first N-type well 130.
In the triple well structure, it is important that the base region 144 and the sidewall region 142 of the second N-type well 140 completely enclose the second P-type well 120, to completely electrically isolate the second P-type well 120 from the first P-type well 110. In the fabrication methods of the prior art, a misalignment can occur between photolithographic steps. Such can result instead in forming a base region 144', shown by dashed lines, instead of base region 144. In that case, overlap of the base region 144' and the sidewall region 142 is not complete, which causes an electrical short between the first P-type well 110 and the second P-type well 120.
Another problem in the prior art is that the photolithography process must be performed at least four times, because of the geometry of one well enclosing the other. This renders the overall process complicated and expensive.